The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing at least one stacked semiconductor material nanosheet device that is devoid of a parasitic transistor beneath the at least one stacked semiconductor nanosheet device. The present application also relates to a method of forming such a semiconductor structure.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. One type of non-planar semiconductor device that has been touted as a viable option beyond the 7 nm technology node is a nanosheet containing device. By “nanosheet containing device” it is meant that the device contains one or more layers of semiconductor channel material portions having a vertical thickness that is substantially less than its width.
Nanosheet formation relies on the selective removal of one semiconductor material (e.g., silicon) to another semiconductor material (e.g., a silicon germanium alloy) to form suspended nanosheets for gate-all-around devices. In the prior art, source/drain (S/D) regions for nanosheet containing devices are formed by epitaxial growth of a semiconductor material upwards from an exposed surface of the semiconductor substrate and from sidewalls of each nanosheet. Such a bottom up epitaxial growth of the S/D regions from the semiconductor substrate creates an undesirable parasitic transistor under the nanosheet stack. There is a need for providing nanosheet containing devices that avoid such a bottom up epitaxial growth of the S/D regions.